Datasheet

Section 6 Bus Controller
Rev.6.00 Sep. 27, 2007 Page 145 of 1268
REJ09B0220-0600
6.1.2 Block Diagram
Figure 6.1 shows a block diagram of the bus controller.
Area decoder
Bus
controller
ABWCR
ASTCR
BCRH
BCRL
Internal
address bus
CS0 to CS7
External bus control signals
BREQ
BACK
BREQO
Internal control
signals
Wait
controller
WCRH
WCRL
Bus mode signal
DRAM
controller*
RTCNT
RTCOR
DRAMCR
MCR
Bus arbiter
CPU bus request signal
DTC bus request signal
DMAC bus request signal*
CPU bus acknowledge signal
DTC bus acknowledge signal
DMAC bus acknowledge signal*
External DRAM
signals*
Note: * Not supported in the H8S/2321.
WAIT
Internal data bus
Figure 6.1 Block Diagram of Bus Controller