Datasheet

Section 5 Interrupt Controller
Rev.6.00 Sep. 27, 2007 Page 135 of 1268
REJ09B0220-0600
(14)(12)(10)(8)
(6)(4)(2)
(1) (5)
(7) (9) (11) (13)
Interrupt handling routine instruction prefetch
Internal operation
Vector fetchStack
Instruction prefetch
Internal operation
Interrupt acceptance
Interrupt level determination Wait for end of instruction
Interrupt request signal
Internal address bus Internal read signal Internal write signal Internal data bus
φ
(3)
(1) (2), (4) (3) (5) (7)
Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) Instruction code (Not executed.) Instruction prefetch address (Not executed.) SP-2 SP-4
Saved PC and saved CCR Vector address Interrupt handling routine start address (vector address contents) Interrupt handling routine start address ((13) = (10), (12)) First instruction of interrupt handling routine
(6), (8) (9), (11) (10), (12) (13) (14)
Figure 5.7 Interrupt Exception Handling