Datasheet

Section 5 Interrupt Controller
Rev.6.00 Sep. 27, 2007 Page 126 of 1268
REJ09B0220-0600
Interrupt Source
Origin of
Interrupt
Source
Vector
Number
Vector
Address
*
1
IPR
Priority
DTC
Activa-
tion
DMAC
*
2
Activa-
tion
DEND0A (channel
0/channel 0A transfer
end)
*
3
DMAC 72 H'0120 IPRJ6 to
IPRJ4
High —
DEND0B (channel 0B
transfer end)
*
3
73 H'0124
—
DEND1A (channel
1/channel 1A transfer
end)
*
3
74 H'0128 —
DEND1B (channel 1B
transfer end)
*
3
75 H'012C
—
Reserved — 76
77
78
79
H'0130
H'0134
H'0138
H'013C
— —
ERI0 (receive error 0) 80 H'0140 IPRJ2 to — —
RXI0 (reception data
full 0)
SCI
channel 0
81 H'0144
IPRJ0
TXI0 (transmit data
empty 0)
82 H'0148
TEI0 (transmit end 0) 83 H'014C — —
ERI1 (receive error 1) 84 H'0150 IPRK6 to — —
RXI1 (reception data
full 1)
SCI
channel 1
85 H'0154
IPRK4
TXI1 (transmit data
empty 1)
86 H'0158
TEI1 (transmit end 1) 87 H'015C — —
ERI2 (receive error 2) 88 H'0160 IPRK2 to — —
RXI2 (reception data
full 2)
SCI
channel 2
89 H'0164
IPRK0
—
TXI2 (transmit data
empty 2)
90 H'0168 —
TEI2 (transmit end 2) 91 H'016C Low — —
Notes: 1. Lower 16 bits of the start address.
2. The DMAC is not supported in the H8S/2321.
3. Reserved in the H8S/2321.