Datasheet

Section 5 Interrupt Controller
Rev.6.00 Sep. 27, 2007 Page 117 of 1268
REJ09B0220-0600
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)
ISCRH
Bit : 15 14 13 12 11 10 9 8
IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
ISCRL
Bit : 7 6 5 4 3 2 1 0
IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
ISCR (composed of ISCRH and ISCRL) is a 16-bit readable/writable register that selects rising
edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0.
ISCR is initialized to H'0000 by a reset and in hardware standby mode.
Bits 15 to 0—IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to IRQ0 Sense Control A
and B (IRQ0SCA, IRQ0SCB)
Bits 15 to 0
IRQ7SCB to
IRQ0SCB
IRQ7SCA to
IRQ0SCA Description
0 0 Interrupt request generated at IRQ7 to IRQ0 input low level
(Initial value)
1 Interrupt request generated at falling edge of IRQ7 to IRQ0 input
1 0 Interrupt request generated at rising edge of IRQ7 to IRQ0 input
1 Interrupt request generated at both falling and rising edges of
IRQ7 to IRQ0 input