Datasheet

Section 5 Interrupt Controller
Rev.6.00 Sep. 27, 2007 Page 112 of 1268
REJ09B0220-0600
5.1.2 Block Diagram
A block diagram of the interrupt controller is shown in figure 5.1.
NMI input
IRQ input
Internal interrupt
request
SWDTEND to TEI
INTM1 INTM0
NMIEG
NMI input unit
IRQ input unit
ISR
ISCR IER
IPR
Interrupt controller
Priority
determination
Interrupt
request
Vector
number
I
I2 to I0
CCR
EXR
CPU
Legend:
ISCR: IRQ sense control register
IER: IRQ enable register
ISR: IRQ status register
IPR: Interrupt priority register
SYSCR: System control register
SYSCR
Figure 5.1 Block Diagram of Interrupt Controller