Datasheet

Section 5 Interrupt Controller
Rev.6.00 Sep. 27, 2007 Page 111 of 1268
REJ09B0220-0600
Section 5 Interrupt Controller
5.1 Overview
5.1.1 Features
The chip controls interrupts by means of an interrupt controller. The interrupt controller has the
following features. This chapter assumes the maximum number of interrupt sources available in
these series—nine external interrupts and 52 internal interrupts.
• Two interrupt control modes
⎯ Either of two interrupt control modes can be set by means of the INTM1 and INTM0 bits
in the system control register (SYSCR)
• Priorities settable with IPRs
⎯ Interrupt priority registers (IPRs) are provided for setting interrupt priorities. Eight priority
levels can be set for each module for all interrupts except NMI
⎯ NMI is assigned the highest priority level of 8, and can be accepted at all times
• Independent vector addresses
⎯ All interrupt sources are assigned independent vector addresses, making it unnecessary for
the source to be identified in the interrupt handling routine
• Nine external interrupt pins
⎯ NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling
edge can be selected for NMI
⎯ Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ7
to IRQ0
• DTC and DMAC
*
control
⎯ DTC and DMAC
*
activation is controlled by means of interrupts
Note: * The DMAC is not supported in the H8S/2321.