Datasheet

Section 4 Exception Handling
Rev.6.00 Sep. 27, 2007 Page 107 of 1268
REJ09B0220-0600
4.4 Interrupts
Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and
52 internal sources in the on-chip supporting modules. Figure 4.3 classifies the interrupt sources
and the number of interrupts of each type.
The on-chip supporting modules that can request interrupts include the watchdog timer (WDT),
refresh timer
*
, 16-bit timer-pulse unit (TPU), 8-bit timer, serial communication interface (SCI),
data transfer controller (DTC), DMA controller (DMAC)
*
, and A/D converter. Each interrupt
source has a separate vector address.
NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The
interrupt controller has two interrupt control modes and can assign interrupts other than NMI to
eight priority/mask levels to enable multiplexed interrupt control.
For details of interrupts, see section 5, Interrupt Controller.
Note: * The refresh timer and DMAC are not supported in the H8S/2321.
Interrupts
External
interrupts
Internal
interrupts
NMI (1)
IRQ7 to IRQ0 (8)
WDT
*1
(1)
Refresh timer
*2 *3
(1)
TPU (26)
8-bit timer (6)
SCI (12)
DTC (1)
DMAC (4)
*3
A/D converter (1)
Notes: Numbers in parentheses are the numbers of interrupt sources.
1. When the watchdog timer is used as an interval timer, it generates an interrupt request
at each counter overflow.
2. When the refresh timer is used as an interval timer, it generates an interrupt request at
each compare match.
3. The refresh timer and DMAC are not supported in the H8S/2321.
Figure 4.3 Interrupt Sources and Number of Interrupts