Datasheet

Appendix C I/O Port Block Diagrams
Rev.6.00 Sep. 27, 2007 Page 1235 of 1268
REJ09B0220-0600
R
P61DDR
C
QD
Reset
WDDR6
Reset
WDR6
R
P61DR
C
QD
P6
1
RDR6
RPOR6
Bus controller
Chip select
DMA controller
*
DMA transfer end enable
Legend:
WDDR6: Write to P6DDR
WDR6: Write to P6DR
RDR6: Read P6DR
RPOR6: Read port 6
CS25E: CS25 enable
Note: * The DMAC is not supported in the H8S/2321.
Mode 7
Modes
4 to 6
Internal data bus
CS25E
DMA transfer end
Figure C.6 (b) Port 6 Block Diagram (Pin P6
1
)