Datasheet

Appendix C I/O Port Block Diagrams
Rev.6.00 Sep. 27, 2007 Page 1234 of 1268
REJ09B0220-0600
C.6 Port 6
R
P60DDR
C
QD
Reset
WDDR6
Mode 7
Modes
4 to 6
Reset
WDR6
R
P60DR
C
QD
P6
0
RDR6
RPOR6
DMA controller
*
Bus controller
Chip select
DMA request input
Legend:
WDDR6: Write to P6DDR
WDR6: Write to P6DR
RDR6: Read P6DR
RPOR6: Read port 6
CS25E: CS25 enable
Note: * The DMAC is not supported in the H8S/2321.
Internal data bus
CS25E
Figure C.6 (a) Port 6 Block Diagram (Pin P6
0
)