Datasheet

Appendix B Internal I/O Registers
Rev.6.00 Sep. 27, 2007 Page 1205 of 1268
REJ09B0220-0600
TSR0—Timer Status Register 0 H'FFD5 TPU0
7
—
1
—
6
—
1
—
5
—
0
—
4
TCFV
0
R/(W)
*
3
TGFD
0
R/(W)
*
0
TGFA
0
R/(W)
*
2
TGFC
0
R/(W)
*
1
TGFB
0
R/(W)
*
Note: * Can only be written with 0 for flag clearing.
0
Overflow Flag
1
0
Input Capture/Output Compare Flag D
1
0
Input Capture/Output Compare Flag C
1
0
Input Capture/Output Compare Flag B
1
0 [Clearing conditions]
• When DTC is activated by TGIA interrupt while
DISEL bit of MRB in DTC is 0
• When DMAC*
1
is activated by TGIA interrupt
while DTA bit of DMABCR in DMAC*
1
is 1
• When 0 is written to TGFA after reading
TGFA = 1
Input Capture/Output Compare Flag A
Note: 1. The DMAC is not supported in the H8S/2321.
1
Bit
Initial value
Read/Write
:
:
:
[Setting conditions]
• When TCNT = TGRA while TGRA is functioning
as output compare register
• When TCNT value is transferred to TGRA by
input capture signal while TGRA is functioning
as input capture register
[Clearing conditions]
• When DTC is activated by TGIB interrupt while DISEL bit
of MRB in DTC is 0
• When 0 is written to TGFB after reading TGFB = 1
[Setting conditions]
• When TCNT = TGRB while TGRB is functioning as
output compare register
• When TCNT value is transferred to TGRB by input
capture signal while TGRB is functioning as input capture
register
[Clearing conditions]
• When DTC is activated by TGIC interrupt while DISEL bit of MRB in
DTC is 0
• When 0 is written to TGFC after reading TGFC = 1
[Setting conditions]
• When TCNT = TGRC while TGRC is functioning as output compare
register
• When TCNT value is transferred to TGRC by input capture signal
while TGRC is functioning as input capture register
[Clearing conditions]
• When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC
is 0
• When 0 is written to TGFD after reading TGFD = 1
[Setting conditions]
• When TCNT = TGRD while TGRD is functioning as output compare register
• When TCNT value is transferred to TGRD by input capture signal while
TGRD is functioning as input capture register
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
[Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000 )