Datasheet

Appendix B Internal I/O Registers
Rev.6.00 Sep. 27, 2007 Page 1189 of 1268
REJ09B0220-0600
TCSR0—Timer Control/Status Register 0 H'FFB2 8-Bit Timer Channel 0
TCSR1—Timer Control/Status Register 1 H'FFB3 8-Bit Timer Channel 1
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
0
R/(W)*
4
—
1
—
3
OS3
0
R/W
0
OS0
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
TCSR1
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
0
R/(W)*
4
ADTE
0
R/W
3
OS3
0
R/W
0
OS0
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
TCSR0
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
0
1
Compare Match Flag B
0
1
Compare Match Flag A
0 [Clearing condition]
When 0 is written to OVF after reading OVF = 1
1
Timer Overflow Flag
0
1
A/D converter start requests by compare match A are disabled
A/D converter start requests by compare match A are enabled
A/D Trigger Enable (TCSR0 only)
0
1
No change when compare match B occurs
0 is output when compare match B occurs
1 is output when compare match B occurs
0
1
0
1
Output Select
Bit
Initial value
Read/Write
:
:
:
Bit
Initial value
Read/Write
:
:
:
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
[Clearing conditions]
• When 0 is written to CMFA after reading CMFA = 1
• When the DTC is activated by a CMIA interrupt, while the DISEL bit of MRB in DTC is 0
[Setting condition]
When TCNT matches TCORA
[Clearing conditions]
• When 0 is written to CMFB after reading CMFB = 1
• When the DTC is activated by a CMIB interrupt, while the DISEL bit of MRB in DTC is 0
[Setting condition]
When TCNT matches TCORB
Output is inverted when compare match B
occurs (toggle output)
0 No change when compare
match A occurs
0
Output Select
Output is inverted when
compare match A
occurs (toggle output)
1 is output when compare
match A occurs
0 is output when compare
match A occurs
1
1
0
1