Datasheet

Appendix B Internal I/O Registers
Rev.6.00 Sep. 27, 2007 Page 1183 of 1268
REJ09B0220-0600
ADCSR—A/D Control/Status Register H'FF98 A/D Converter
[Clearing conditions]
• When 0 is written to the ADF flag after reading ADF = 1
• When the DMAC
*2
or DTC is activated by an ADI interrupt, and ADDR is read
7
ADF
0
R/(W)
*1
6
ADIE
0
R/W
5
ADST
0
R/W
4
SCAN
0
R/W
3
CKS
0
R/W
0
CH0
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W
Notes: 1. Can only be written with 0 for flag clearing.
2. The DMAC is not supported in the H8S/2321.
0
1
A/D conversion end interrupt request disabled
A/D conversion end interrupt request enabled
A/D Interrupt Enable
0
1
Single mode
Scan mode
Scan Mode
0
1
A/D conversion stopped
A/D Start
0
A/D End Flag
CH1
0
1
0
1
CH0
0
1
0
1
0
1
0
1
Single Mode
(SCAN = 0)
AN
0
AN
0
, AN
1
AN
0
to AN
2
AN
0
to AN
3
AN
4
AN
4
, AN
5
AN
4
to AN
6
AN
4
to AN
7
Bit
Initial value
Read/Write
:
:
:
• Single mode: A/D conversion is started. Cleared to 0
automatically when conversion ends
• Scan mode: A/D conversion is started. Conversion continues
sequentially on the selected channels until ADST is cleared to
0 by software, a reset, or transition to standby mode or
module stop mode
[Setting conditions]
• Single mode: When A/D conversion ends
• Scan mode: When A/D conversion ends on all specified channels
1
CH2
0
1
Group
Selection
Channel
Selection
AN
0
(Initial value)
AN
1
AN
2
AN
3
AN
4
AN
5
AN
6
AN
7
Scan Mode
(SCAN = 1)
Clock Select
Note: CKS is used in combination with bit 3 (CKS1)
of ADCR.
See ADCR—A/D Control Register
H'FF99 A/D Converter.
Channel Select
Note: These bits select the analog input channels.
Ensure that conversion is halted (ADST = 0)
before making a channel selection.