Datasheet

Appendix B Internal I/O Registers
Rev.6.00 Sep. 27, 2007 Page 1134 of 1268
REJ09B0220-0600
SCKCR—System Clock Control Register H'FF3A Clock Pulse Generator
7
PSTOP
0
R/W
6
—
0
R/W
5
DIV
0
R/W
4
—
0
—
3
—
0
—
0
SCK0
0
R/W
2
SCK2
0
R/W
1
SCK1
0
R/W
0
1
PSTOP Normal Operation
φ output
Fixed high
High impedance
High impedance
Fixed high
Fixed high
φ Clock Output Control
System Clock Select
SCK0SCK1SCK2
DIV = 0 DIV = 1
0
1
0
1
0
1
0
1
0
1
0
1
—
Bus master is in high-speed mode
Medium-speed clock is
φ /2
Medium-speed clock is
φ /4
Medium-speed clock is
φ /8
Medium-speed clock is
φ /16
Medium-speed clock is
φ /32
—
Bus master is in high-speed mode
Clock supplied to entire chip is
φ /2
Clock supplied to entire chip is
φ /4
Clock supplied to entire chip is
φ /8
—
—
—
φ output
Fixed high
Sleep Mode
Bit
Initial value
Read/Write
:
:
:
Software
Standby Mode
Hardware
Standby Mode
Division
Ratio
Select
Reserved
Only 0 should be
written to this bit