Datasheet

Appendix B Internal I/O Registers
Rev.6.00 Sep. 27, 2007 Page 1133 of 1268
REJ09B0220-0600
SYSCR—System Control Register H'FF39 MCU
7
—
0
R/W
6
—
0
—
5
INTM1
0
R/W
4
INTM0
0
R/W
3
NMIEG
0
R/W
0
RAME
1
R/W
2
LWROD
0
R/W
1
IRQPAS
0
R/W
Bit
Initial value
Read/Write
:
:
:
Reserved
Only 0 should be written to this bit
RAM Enable
0 On-chip RAM disabled
1 On-chip RAM enabled
NMI Input Edge Select
0 Falling edge
1 Rising edge
Interrupt Control Mode Selection
0
1
Interrupt control mode 00
1
0
1
Setting prohibited
Interrupt control mode 2
Setting prohibited
LWR Output Disable
0PF
3
is designated as LWR output pin
1PF
3
is designated as I/O port, and
does not function as LWR output pin
IRQ Port Switching Select
0 IRQ
4
to IRQ
7
can be input
from PA
4
to PA
7
1 IRQ
4
to IRQ
7
can be input
from P5
0
to P5
3
Note: IRQ
4
to IRQ
7
input is always
performed from only one of
the ports.