Datasheet

Appendix B Internal I/O Registers
Rev.6.00 Sep. 27, 2007 Page 1131 of 1268
REJ09B0220-0600
DTVECR—DTC Vector Register H'FF37 DTC
7
SWDTE
0
R/W
6
DTVEC6
0
R/(W)*
5
DTVEC5
0
R/(W)*
4
DTVEC4
0
R/(W)*
3
DTVEC3
0
R/(W)*
0
DTVEC0
0
R/(W)*
2
DTVEC2
0
R/(W)*
1
DTVEC1
0
R/(W)*
DTVEC6 to DTVEC 0 bits can be written to when SWDTE = 0.Note: *
DTC Software Activation Enable
0
1
DTC software activation is disabled
[Clearing conditions]
• When the DISEL bit is 0 and the specified number of transfers have
not ended
• When SWDTEND is requested to the CPU, then 0 is written to the
SWDTE bit
DTC software activation is enabled
[Holding conditions]
• When the DISEL bit is 1 and data transfer has ended
• When the specified number of transfers have ended
• During data transfer due to software activation
Sets vector number for DTC software activation
Bit
Initial value
Read/Write
:
:
: