Datasheet

Appendix B Internal I/O Registers
Rev.6.00 Sep. 27, 2007 Page 1124 of 1268
REJ09B0220-0600
DMABCRH — DMA Band Control Register H'FF06 DMAC
(Not supported in H8S/2321)
DMABCRL — DMA Band Control Register H'FF07 DMAC
(Not supported in H8S/2321)
15
FAE1
0
R/W
14
FAE0
0
R/W
13
—
0
R/W
12
—
0
R/W
11
DTA1
0
R/W
8
—
0
R/W
10
—
0
R/W
9
DTA0
0
R/W
Full address mode
Bit
DMABCRH
Initial value
Read/Write
:
:
:
:
0
1
Short address mode
Full address mode
Channel 1 Full Address Enable
0
1
Short address mode
Full address mode
Channel 0 Full Address Enable
0 Clearing of selected internal interrupt source
at time of DMA transfer is disabled
Channel 1 Data Transfer Acknowledge
1
Clearing of selected internal interrupt source
at time of DMA transfer is enabled
0 Clearing of selected internal interrupt source
at time of DMA transfer is disabled
Channel 0 Data Transfer Acknowledge
Reserved
Only 0 should be written to this bit
Reserved
Only 0 should be written to this bit
Reserved
Only 0 should be written to these bits
1
Clearing of selected internal interrupt source
at time of DMA transfer is enabled
(Continued on next page)