Datasheet

Appendix B Internal I/O Registers
Rev.6.00 Sep. 27, 2007 Page 1120 of 1268
REJ09B0220-0600
DMATCR—DMA Terminal Control Register H'FF01 DMAC
(Not supported in H8S/2321)
7
—
0
—
6
—
0
—
5
TEE1
0
R/W
4
TEE0
0
R/W
3
—
0
—
0
—
0
—
2
—
0
—
1
—
0
—
Bit
DMATCR
Initial value
Read/Write
:
:
:
:
Transfer End Enable 1
0
1
Transfer End Enable 0
0
1
TEND
0
pin output disabled
TEND
0
pin output enabled
TEND
1
pin output disabled
TE
ND
1
pin output enabled