Datasheet

Appendix B Internal I/O Registers
Rev.6.00 Sep. 27, 2007 Page 1110 of 1268
REJ09B0220-0600
DRAMCR—DRAM Control Register H'FED7 Bus Controller
(Not supported in H8S/2321)
7
RFSHE
0
R/W
6
RCW
0
R/W
5
RMODE
0
R/W
4
CMF
0
R/W
3
CMIE
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Bit
Initial value
Read/Write
:
:
:
Refresh Control
0
1
Refresh control is not performed
Refresh control is performed
RAS-CAS Wait
0 Wait state insertion in CAS-before-RAS refreshing disabled
RAS falls in T
r
cycle
Refresh Mode
0
1
Self-refreshing is not performed in software standby mode
Self-refreshing is performed in software standby mode
Compare Match Flag
0
1
[Clearing condition]
When 0 is written to CMF after reading CMF = 1
[Setting condition]
When RTCNT = RTCOR
Compare Match Interrupt Enable
0
1
Interrupt request (CMI) by CMF flag disabled
Interrupt request (CMI) by CMF flag enabled
Refresh Counter Clock Select
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Count operation disabled
Count uses
φ/2
Count uses
φ/8
Count uses
φ/32
Count uses
φ/128
Count uses
φ/512
Count uses
φ/2048
Count uses
φ/4096
One wait state inserted in CAS-before-RAS refreshing
RAS falls in T
c1
cycle
1