Datasheet

Appendix B Internal I/O Registers
Rev.6.00 Sep. 27, 2007 Page 1109 of 1268
REJ09B0220-0600
MCR—Memory Control Register H'FED6 Bus Controller
(Not supported in H8S/2321)
7
TPC
0
R/W
6
BE
0
R/W
5
RCDM
0
R/W
4
—
0
R/W
3
MXC1
0
R/W
0
RLW0
0
R/W
2
MXC0
0
R/W
1
RLW1
0
R/W
Bit
Initial value
Read/Write
:
:
:
TP Cycle Control
0
1
1-state precharge cycle is inserted
2-state precharge cycle is inserted
Burst Access Enable
0
1
Burst disabled (always full access)
RAS Down Mode
0
1
RAS up mode selected for DRAM interface
RAS down mode selected for DRAM interface
Reserved
Multiplex Shift Count
0
1
8-bit shift
9-bit shift
10-bit shift
—
0
1
0
1
Refresh Cycle Wait Control
0
1
No wait state inserted
1 wait state inserted
2 wait states inserted
3 wait states inserted
0
1
0
1
For DRAM space access, access in fast page mode