Datasheet

Appendix B Internal I/O Registers
Rev.6.00 Sep. 27, 2007 Page 1108 of 1268
REJ09B0220-0600
BCRL—Bus Control Register L H'FED5 Bus Controller
7
BRLE
0
R/W
6
BREQOE
0
R/W
5
EAE
1
R/W
4
—
1
R/W
3
DDS
1
R/W
0
WAITE
0
R/W
2
—
1
R/W
1
WDBE
0
R/W
Bit
Initial value
Read/Write
:
:
:
Bus Release Enable
0
1
External bus release disabled
External bus release enabled
BREQO Pin Enable
0
1
BREQO output disabled
BREQO
*
output enabled
0
1
• In the H8S/2329B, H8S/2328
*3
, and H8S/2326, addresses H'010000 to
H'03FFFF
*2
are on-chip ROM
• In the H8S/2327, addresses H'010000 to H'01FFFF are on-chip ROM,
and addresses H'020000 to H'03FFFF are a reserved area
*1
• In the H8S/2323, addresses H'010000 to H'03FFFF are a reserved area
*1
Addresses H'010000 to H'03FFFF
*2
are external addresses
in external expanded mode or reserved area
*2
in single-chip mode
Reserved
Only 1 should be written to this bit
External Addresses H'010000 to H'03FFFF Enable
Write Data Buffer Enable
0
1
WAIT Pin Enable
0
1
Wait input by WAIT
pin
*
disabled
Wait input by WAIT
pin
*
enabled
Write data buffer function
not used
Write data buffer function
used
Reserved
Only 1 should be written to this bit
Notes: 1. Do not access a reserved area.
2. Address H'010000 to H'03FFFF in the H8S/2328.
Address H'010000 to H'05FFFF in the H8S/2329B.
Address H'010000 to H'07FFFF in the H8S/2326.
3. H8S/2328B in flash memory version.
DACK Timing Select
When DMAC single address transfer is performed in
DRAM space, full access is always executed. DACK
signal goes low from Tr or T1 cycle
0
1 Burst access is possible when DMAC single address
transfer is performed in DRAM space. DACK signal
goes low from Tc1 or T2 cycle
Note: * The WAIT input pin
can be switched
between PF
2
and
P5
3
by means of
WAITPS.
Note: * The BREQO output pin can be switched between
PF
2
and P5
3
by means of BREQOPS.
Note: In the H8S/2321 this bit is reserved and should only
be written with 1.