Datasheet

Section 3 MCU Operating Modes
Rev.6.00 Sep. 27, 2007 Page 82 of 1268
REJ09B0220-0600
Bit 1—IRQ Port Switching Select (IRQPAS): Selects switching of input pins for IRQ
4
to IRQ
7
.
IRQ
4
to IRQ
7
input is always performed from one of the ports.
Bit 1
IRQPAS Description
0 PA
4
to PA
7
are used for IRQ
4
to IRQ
7
input (Initial value)
1 P5
0
to P5
3
are used for IRQ
4
to IRQ
7
input
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Bit 0
RAME Description
0 On-chip RAM is disabled
1 On-chip RAM is enabled (Initial value)
3.2.3 System Control Register 2 (SYSCR2) (F-ZTAT Version Only)
Bit : 7 6 5 4 3 2 1 0
— — — — FLSHE — — —
Initial value : 0 0 0 0 0 0 0 0
R/W : — — — — R/W — — — (R/W)
*
Note: * R/W in the H8S/2329B F-ZTAT.
SYSCR2 is an 8-bit readable/writable register that performs on-chip flash memory control.
SYSCR2 is initialized to H'00 by a reset, and in hardware standby mode.
Bits 7 to 4—Reserved: These bits are always read as 0, and cannot be modified.
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash
memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). For details, see section 19,
ROM.