Datasheet

Appendix B Internal I/O Registers
Rev.6.00 Sep. 27, 2007 Page 1103 of 1268
REJ09B0220-0600
IPRA — Interrupt Priority Register A H'FEC4 Interrupt Controller
IPRB — Interrupt Priority Register B H'FEC5 Interrupt Controller
IPRC — Interrupt Priority Register C H'FEC6 Interrupt Controller
IPRD — Interrupt Priority Register D H'FEC7 Interrupt Controller
IPRE — Interrupt Priority Register E H'FEC8 Interrupt Controller
IPRF — Interrupt Priority Register F H'FEC9 Interrupt Controller
IPRG — Interrupt Priority Register G H'FECA Interrupt Controller
IPRH — Interrupt Priority Register H H'FECB Interrupt Controller
IPRI — Interrupt Priority Register I H'FECC Interrupt Controller
IPRJ — Interrupt Priority Register J H'FECD Interrupt Controller
IPRK — Interrupt Priority Register K H'FECE Interrupt Controller
7
—
0
—
6
IPR6
1
R/W
5
IPR5
1
R/W
4
IPR4
1
R/W
3
—
0
—
0
IPR0
1
R/W
2
IPR2
1
R/W
1
IPR1
1
R/W
Set priority (levels 7 to 0) for interrupt sources
IPRA
IPRB
IPRC
IPRD
IPRE
IPRF
IPRG
IPRH
IPRI
IPRJ
IPRK
Register
Bits
IRQ0
IRQ2
IRQ3
IRQ6
IRQ7
WDT
—
*1
TPU channel 0
TPU channel 2
TPU channel 4
8-bit timer channel 0
DMAC
*2
SCI channel 1
IRQ1
IRQ4
IRQ5
DTC
Refresh timer
*2
A/D converter
TPU channel 1
TPU channel 3
TPU channel 5
8-bit timer channel 1
SCI channel 0
SCI channel 2
6 to 4 2 to 0
Correspondence between Interrupt Sources and IPR Settings
Notes: 1.
2.
Reserved bits.
Reserved bit in the H8S/2321.
Bit
Initial value
Read/Write
:
:
: