Datasheet

Section 3 MCU Operating Modes
Rev.6.00 Sep. 27, 2007 Page 80 of 1268
REJ09B0220-0600
3.1.3 Register Configuration
The H8S/2329 Group and H8S/2328 Group have a mode control register (MDCR) that indicates
the inputs at the mode pins (MD
2
to MD
0
), and a system control register (SYSCR) and a system
control register 2 (SYSCR2)
*
2
that control the operation of the chip. Table 3.3 summarizes these
registers.
Table 3.3 Registers
Name Abbreviation R/W Initial Value Address
*
1
Mode control register MDCR R Undefined H'FF3B
System control register SYSCR R/W H'01 H'FF39
System control register 2
*
2
SYSCR2 R/W H'00 H'FF42
Notes: 1. Lower 16 bits of the address.
2. The SYSCR2 register can only be used in the F-ZTAT versions. In the mask ROM and
ROMless versions this register will return an undefined value if read, and cannot be
modified.
3.2 Register Descriptions
3.2.1 Mode Control Register (MDCR)
Bit : 7 6 5 4 3 2 1 0
— — — — — MDS2 MDS1 MDS0
Initial value : 1 0 0 0 0 —
*
—
*
—
*
R/W : — — — — — R R R
Note: * Determined by pins MD
2
to MD
0
.
MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2329
Group and H8S/2328 Group chip.
Bit 7—Reserved: This bit is always read as 1, and cannot be modified.
Bits 6 to 3—Reserved: These bits are always read as 0, and cannot be modified.
Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins
MD
2
to MD
0
(the current operating mode). Bits MDS2 to MDS0 correspond to pins MD
2
to MD
0
.
MDS2 to MDS0 are read-only bits, and cannot be written to. The mode pin (MD
2
to MD
0
) input
levels are latched into these bits when MDCR is read. These latches are canceled by a reset.