Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFP 128 (14x20) 16-Bit 25 MHz I/O number 86

1101

Appendix B Internal I/O Registers

Rev.6.00 Sep. 27, 2007 Page 1078 of 1268

REJ09B0220-0600

MRB—DTC Mode Register B H'F800—H'FBFF DTC

CHNE

Undefined

—

DISEL

Undefined

—

CHNS

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Bit

Initial value

Read/Write

DTC Chain Transfer Enable

DTC Chain Transfer Select

CHNE

CHNS

—

Description

No chain transfer. (At end of DTC data

transfer, DTC waits for activation)

Chain transfer every time

Chain transfer only when transfer counter = 0

DTC Interrupt Select

Reserved

Only 0 should be written to these bits

After DTC data transfer ends, the CPU interrupt is

disabled unless the transfer counter is 0

After DTC data transfer ends, the CPU interrupt is enabled

SAR—DTC Source Address Register H'F800—H'FBFF DTC

Bit

Initial value

Read/Write

22 21 20 19 43210- - -

- - -

Specifies DTC transfer data source address

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

—————

DAR—DTC Destination Address Register H'F800—H'FBFF DTC

23Bit

Initial value

Read/Write

22 21 20 19 43210- - -

- - -

Specifies DTC transfer data destination address

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—