Datasheet

Appendix B Internal I/O Registers
Rev.6.00 Sep. 27, 2007 Page 1075 of 1266
REJ09B0220-0600
Module Register Abbreviation R/W Initial Value Address
*
1
Port C Port C data direction register PCDDR W H'00 H'FEBB
Port C data register PCDR R/W H'00 H'FF6B
Port C register PORTC R Undefined H'FF5B
Port C MOS pull-up control register PCPCR R/W H'00 H'FF72
Port D Port D data direction register PDDDR W H'00 H'FEBC
Port D data register PDDR R/W H'00 H'FF6C
Port D register PORTD R Undefined H'FF5C
Port D MOS pull-up control register PDPCR R/W H'00 H'FF73
Port E Port E data direction register PEDDR W H'00 H'FEBD
Port E data register PEDR R/W H'00 H'FF6D
Port E register PORTE R Undefined H'FF5D
Port E MOS pull-up control register PEPCR R/W H'00 H'FF74
Port F Port F data direction register PFDDR W H'80/H'00
*
20
H'FEBE
Port F data register PFDR R/W H'00 H'FF6E
Port F register PORTF R Undefined H'FF5E
Port function control register 2 PFCR2 R/W H'30 H'FFAC
System control register SYSCR R/W H'01 H'FF39
Port G Port G data direction register PGDDR W H'10/H'00
*
20
*
21
H'FEBF
Port G data register PGDR R/W H'00
*
21
H'FF6F
Port G register PORTG R Undefined
*
21
H'FF5F
Port function control register 2 PFCR2 R/W H'30 H'FFAC
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written for flag clearing.
3. Registers in the DTC cannot be read or written to directly.
4. Located as register information in on-chip RAM addresses H'EBC0 to H'EFBF. Cannot
be located in external memory space. Do not clear the RAME bit in SYSCR to 0 when
using the DTC.
5. Determined by the MCU operating mode.
6. Reserved in the H8S/2321.
7. The DMAC is not supported in the H8S/2321.
8. Bits used for pulse output cannot be written to.