Datasheet

Appendix B Internal I/O Registers
Rev.6.00 Sep. 27, 2007 Page 1067 of 1266
REJ09B0220-0600
Module Register Abbreviation R/W Initial Value Address
*
1
DTC DTC mode register A MRA —
*
3
Undefined —
*
4
DTC mode register B MRB —
*
3
Undefined —
*
4
DTC source address register SAR —
*
3
Undefined —
*
4
DTC destination address register DAR —
*
3
Undefined —
*
4
DTC transfer count register A CRA —
*
3
Undefined —
*
4
DTC transfer count register B CRB —
*
3
Undefined —
*
4
DTC enable register DTCER R/W H'00 H'FF30 to
H'FF35
DTC vector register DTVECR R/W H'00 H'FF37
Module stop control register MSTPCR R/W H'3FFF H'FF3C
DMAC0 Memory address register 0A MAR0A R/W Undefined H'FEE0
I/O address register 0A IOAR0A R/W Undefined H'FEE4
Transfer count register 0A ETCR0A R/W Undefined H'FEE6
Memory address register 0B MAR0B R/W Undefined H'FEE8
I/O address register 0B IOAR0B R/W Undefined H'FEEC
Transfer count register 0B ETCR0B R/W Undefined H'FEEE
DMAC1
*
7
Memory address register 1A MAR1A R/W Undefined H'FEF0
I/O address register 1A IOAR1A R/W Undefined H'FEF4
Transfer count register 1A ETCR1A R/W Undefined H'FEF6
Memory address register 1B MAR1B R/W Undefined H'FEF8
I/O address register 1B IOAR1B R/W Undefined H'FEFC
Transfer count register 1B ETCR1B R/W Undefined H'FEFE
DMA write enable register DMAWER R/W H'00 H'FF00
DMA terminal control register DMATCR R/W H'00 H'FF01
Both
DMAC
channels
*
7
DMA control register 0A DMACR0A R/W H'00 H'FF02
DMA control register 0B DMACR0B R/W H'00 H'FF03
DMA control register 1A DMACR1A R/W H'00 H'FF04
DMA control register 1B DMACR1B R/W H'00 H'FF05
DMA band control register DMABCR R/W H'0000 H'FF06
Module stop control register MSTPCR R/W H'3FFF H'FF3C