Datasheet

Appendix A Instruction Set
Rev.6.00 Sep. 27, 2007 Page 1054 of 1268
REJ09B0220-0600
Instruction H N Z V C Definition
ROTXL —
0 N = Rm
Z = Rm · Rm–1 ·
......
· R0
C = Dm (1-bit shift) or C = Dm–1 (2-bit shift)
ROTXR — 0 N = Rm
Z = Rm · Rm–1 ·
......
· R0
C = D0 (1-bit shift) or C = D1 (2-bit shift)
RTE Stores the corresponding bits of the result.
RTS — — — — —
SHAL — N = Rm
Z = Rm · Rm–1 ·
......
· R0
V =
Dm · Dm–1 + Dm · Dm–1
(1-bit shift)
V =
Dm · Dm–1 · Dm–2 · Dm · Dm–1 · Dm–2
(2-bit shift)
C = Dm (1-bit shift) or C = Dm–1 (2-bit shift)
SHAR — 0 N = Rm
Z = Rm · Rm–1 ·
......
· R0
C = D0 (1-bit shift) or C = D1 (2-bit shift)
SHLL — 0 N = Rm
Z = Rm · Rm–1 ·
......
· R0
C = Dm (1-bit shift) or C = Dm–1 (2-bit shift)
SHLR — 0 0 N = Rm
Z = Rm · Rm–1 ·
......
· R0
C = D0 (1-bit shift) or C = D1 (2-bit shift)
SLEEP — — — — —
STC — — — — —
STM — — — — —
STMAC Cannot be used in the chip