Datasheet

Section 2 CPU
Rev.6.00 Sep. 27, 2007 Page 75 of 1268
REJ09B0220-0600
2.9.3 On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits
wide, depending on the particular internal I/O register being accessed. Figure 2.16 shows the
access timing for the on-chip supporting modules. Figure 2.17 shows the pin states.
Bus cycle
T
1
T
2
Address
Read data
Write data
Internal read signal
Internal data bus
Internal write signal
Internal data bus
Read
access
Write
access
Internal address bus
φ
Figure 2.16 On-Chip Supporting Module Access Cycle