Datasheet

Appendix A Instruction Set
Rev.6.00 Sep. 27, 2007 Page 1034 of 1268
REJ09B0220-0600
Instruction
Fetch
Branch
Address
Read
Stack
Operation
Byte
Data
Access
Word
Data
Access
Internal
Operation
Instruction Mnemonic I J K L M N
STC STC.B CCR,Rd 1
STC.B EXR,Rd 1
STC.W CCR,@ERd 2 1
STC.W EXR,@ERd 2 1
STC.W CCR,@(d:16,ERd) 3 1
STC.W EXR,@(d:16,ERd) 3 1
STC.W CCR,@(d:32,ERd) 5 1
STC.W EXR,@(d:32,ERd) 5 1
STC.W CCR,@-ERd 2 1 1
STC.W EXR,@-ERd 2 1 1
STC.W CCR,@aa:16 3 1
STC.W EXR,@aa:16 3 1
STC.W CCR,@aa:32 4 1
STC.W EXR,@aa:32 4 1
STM STM.L (ERn-ERn+1),
@-SP
2 4 1
STM.L (ERn-ERn+2),
@-SP
2 6 1
STM.L (ERn-ERn+3),
@-SP
2 8 1
STMAC STMAC MACH,ERd Cannot be used in the chip
STMAC MACL,ERd
SUB SUB.B Rs,Rd 1
SUB.W #xx:16,Rd 2
SUB.W Rs,Rd 1
SUB.L #xx:32,ERd 3
SUB.L ERs,ERd 1
SUBS SUBS #1/2/4,ERd 1
SUBX SUBX #xx:8,Rd 1
SUBX Rs,Rd 1
TAS TAS @ERd
*
3
2 2
TRAPA TRAPA #x:2 Advanced 2 2 2/3
*
1
2