Datasheet

Appendix A Instruction Set
Rev.6.00 Sep. 27, 2007 Page 1023 of 1268
REJ09B0220-0600
Table A.4 Number of States per Cycle
Access Conditions
External Device
On-Chip Supporting
Module
8-Bit Bus 16-Bit Bus
Cycle
On-Chip
Memory
8-Bit
Bus
16-Bit
Bus
2-State
Access
3-State
Access
2-State
Access
3-State
Access
Instruction fetch S
I
1 4 2 4 6 + 2m 2 3 + m
Branch address read S
J
Stack operation S
K
Byte data access S
L
2 2 3 + m
Word data access S
M
4 4 6 + 2m
Internal operation S
N
1 1 1 1 1 1 1
Legend:
m: Number of wait states inserted into external device access