Datasheet

Section 2 CPU
Rev.6.00 Sep. 27, 2007 Page 72 of 1268
REJ09B0220-0600
(c) Interrupt control mode 0 (d) Interrupt control mode 2
CCR
PC
(24 bits)
SP
Note: * Ignored when returning.
CCR
PC
(24 bits)
SP
EXR
Reserved*
A
dvanced mode
Figure 2.13 Stack Structure after Exception Handling (Examples)
2.8.4 Program Execution State
In this state the CPU executes program instructions in sequence.
2.8.5 Bus-Released State
This is a state in which the bus has been released in response to a bus request from a bus master
other than the CPU. While the bus is released, the CPU halts.
There is one other bus master in addition to the CPU: the DMA controller (DMAC)
*
and data
transfer controller (DTC).
For further details, refer to section 6, Bus Controller.
Note: * The DMAC is not supported in the H8S/2321.