Datasheet

Appendix A Instruction Set
Rev.6.00 Sep. 27, 2007 Page 987 of 1268
REJ09B0220-0600
Addressing Mode/
Instruction Length (Bytes)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Mnemonic
EXTS TAS MAC CLRMAC LDMAC STMAC
EXTS.W Rd W 2 EXTS.L ERd L 2 TAS @ERd*
3
B 4
MAC @ERn+, @ERm+ CLRMAC LDMAC ERs,MACH LDMAC ERs,MACL STMAC MACH,ERd STMAC MACL,ERd
(<bit 7> of Rd16)→ — — 0 — 1 (<bits 15 to 8> of Rd16) (<bit 15> of ERd32)→ — — 0 — 1 (<bits 31 to 16> of ERd32) @ERd-0→CCR set, (1)→ — — 0 — 4
(<bit 7> of @ERd) [2]
Operation
Condition Code
IHNZVC
Advanced
No. of States
*
1
↔ ↔ ↔
↔ ↔ ↔
Cannot be used in the chip