Datasheet

Appendix A Instruction Set
Rev.6.00 Sep. 27, 2007 Page 979 of 1268
REJ09B0220-0600
Appendix A Instruction Set
A.1 Instruction List
Operand Notation
Rd General register (destination)
*
1
Rs General register (source)
*
1
Rn General register
*
1
ERn General register (32-bit register)
MAC Multiply-and-accumulate register (32-bit register)
*
2
(EAd) Destination operand
(EAs) Source operand
EXR Extended control register
CCR Condition-code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+ Add
– Subtract
× Multiply
÷ Divide
∧ Logical AND
∨ Logical OR
⊕ Logical exclusive OR
→ Transfer from the operand on the left to the operand on the right, or
transition from the state on the left to the state on the right
¬ Logical NOT (logical complement)
( ) < > Contents of operand
:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length
Notes: 1. General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
2. The MAC register cannot be used in the H8S/2329 Group and H8S/2328 Group.