Datasheet

Section 2 CPU
Rev.6.00 Sep. 27, 2007 Page 69 of 1268
REJ09B0220-0600
End of bus request
Bus request
Program execution
state
Bus-released state
Sleep mode
Exception-handling state
External interrupt
Software standby mode
RES = high
Reset state
STBY = high, RES = low
Hardware standby mode
*2
Power-down state
*1
Notes: 1.
2.
From any state except hardware standby mode, a transition to the reset state occurs whenever RES
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
From any state, a transition to hardware standby mode occurs when STBY goes low.
SLEEP
instruction
with
SSBY = 0
SLEEP
instruction
with
SSBY = 1
Interrupt
request
End of bus
request
Bus
request
Request for
exception
handling
End of
exception
handling
Figure 2.12 State Transitions
2.8.2 Reset State
When the RES input goes low all current processing stops and the CPU enters the reset state. All
interrupts are masked in the reset state. Reset exception handling starts when the RES signal
changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details, refer to section 13,
Watchdog Timer.