Datasheet

Section 22 Electrical Characteristics
Rev.6.00 Sep. 27, 2007 Page 972 of 1268
REJ09B0220-0600
(3) Bus Timing
Table 22.17 Bus Timing
Condition B: V
CC
= 3.0 V to 3.6 V, AV
CC
= 3.0 V to 3.6 V, V
ref
= 3.0 V to AV
CC
, V
SS
= AV
SS
=
0 V, φ = 2 MHz to 25 MHz, T
a
= –20°C to 75°C (regular specifications),
T
a
= –40°C to 85°C (wide-range specifications)
Condition B
Item Symbol Min Max Unit Test Conditions
Address delay time t
AD
— 20 ns Figures 22.6 to 22.13
Address setup time t
AS
0.5 × t
cyc
– 15 — ns
Address hold time t
AH
0.5 × t
cyc
– 8 — ns
Precharge time t
PCH
1.5 × t
cyc
– 15 — ns
CS delay time 1 t
CSD1
— 15 ns
CS delay time 2 t
CSD2
— 15 ns
CS delay time 3 t
CSD3
— 20 ns
AS delay time t
ASD
— 15 ns
RD delay time 1 t
RSD1
— 15 ns
RD delay time 2 t
RSD2
— 15 ns
CAS delay time t
CASD
— 15 ns
Read data setup time t
RDS
15 — ns
Read data hold time t
RDH
0 — ns
Read data access time 1 t
ACC1
— 1.0 × t
cyc
– 20 ns
Read data access time 2 t
ACC2
— 1.5 × t
cyc
– 20 ns
Read data access time 3 t
ACC3
— 2.0 × t
cyc
– 20 ns
Read data access time 4 t
ACC4
— 2.5 × t
cyc
– 20 ns
Read data access time 5 t
ACC5
— 3.0 × t
cyc
– 20 ns
Read data access time 6 t
ACC6
— 1.0 × t
cyc
– 20 ns
WR delay time 1 t
WRD1
— 15 ns
WR delay time 2 t
WRD2
— 15 ns
WR pulse width 1 t
WSW1
1.0 × t
cyc
– 15 — ns
WR pulse width 2 t
WSW2
1.5 × t
cyc
– 15 — ns
Write data delay time t
WDD
— 20 ns
Write data setup time t
WDS
0.5 × t
cyc
– 15 — ns
Write data hold time t
WDH
0.5 × t
cyc
– 8 — ns
WR setup time t
WCS
0.5 × t
cyc
– 10 — ns
WR hold time t
WCH
0.5 × t
cyc
– 10 — ns