Datasheet

Section 19 ROM
Rev.6.00 Sep. 27, 2007 Page 753 of 1268
REJ09B0220-0600
19.5.2 Flash Memory Control Register 2 (FLMCR2)
Bit : 7 6 5 4 3 2 1 0
FLER — — — — — — —
Initial value : 0 0 0 0 0 0 0 0
R/W : R — — — — — — —
FLMCR2 is an 8-bit register that controls the flash memory operating modes. FLMCR2 is
initialized to H'00 by a reset, and in hardware standby mode and software standby mode.
When on-chip flash memory is disabled, a read will return H'00 and writes are invalid.
Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on
flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-
protection state.
Bit 7
FLER Description
0 Flash memory is operating normally (Initial value)
Flash memory program/erase protection (error protection) is disabled
[Clearing condition]
Reset or hardware standby mode
1 An error has occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting condition]
See section 19.8.3, Error Protection
Bits 6 to 0—Reserved: These bits cannot be modified and are always read as 0.