Datasheet

Section 14 Serial Communication Interface (SCI)
Rev.6.00 Sep. 27, 2007 Page 607 of 1268
REJ09B0220-0600
14.2.6 Serial Control Register (SCR)
Bit : 7 6 5 4 3 2 1 0
TIE RIE TE RE MPIE TEIE CKE1 CKE0
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output
in asynchronous mode, and interrupt requests, and selection of the serial clock source.
SCR can be read or written to by the CPU at all times.
SCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode and
module stop mode it retains its previous state.
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty interrupt
(TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE
flag in SSR is set to 1.
Bit 7
TIE Description
0 Transmit-data-empty interrupt (TXI) requests disabled
*
(Initial value)
1 Transmit-data-empty interrupt (TXI) requests enabled
Note:* TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then
clearing it to 0, or by clearing the TIE bit to 0.