Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.6.00 Sep. 27, 2007 Page 494 of 1268
REJ09B0220-0600
Examples of Buffer Operation
• When TGR is an output compare register
Figure 10.19 shows an operation example in which PWM mode 1 has been designated for
channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used
in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0
output at compare match B.
As buffer operation has been set, when compare match A occurs the output changes and the
value in buffer register TGRC is simultaneously transferred to timer general register TGRA.
This operation is repeated each time compare match A occurs.
For details of PWM modes, see section 10.4.6, PWM Modes.
TCNT value
TGR0B
H'0000
TGR0C
Time
TGR0A
H'0200 H'0520
TIOCA
H'0200
H'0450
H'0520
H'0450
TGR0A
H'0450H'0200
Transfer
Figure 10.19 Example of Buffer Operation (1)