Datasheet

Section 9 I/O Ports
Rev.6.00 Sep. 27, 2007 Page 437 of 1268
REJ09B0220-0600
Port G Data Register (PGDR)
Bit : 7 6 5 4 3 2 1 0
— — — PG4DR PG3DR PG2DR PG1DR PG0DR
Initial value : Undefined Undefined Undefined 0 0 0 0 0
R/W : — — — R/W R/W R/W R/W R/W
PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG
4
to
PG
0
).
Bits 7 to 5 are reserved; they return an undefined value if read, and cannot be modified.
PGDR is initialized to H'00 (bits 4 to 0) by a reset, and in hardware standby mode. It retains its
prior state in software standby mode.
Port G Register (PORTG)
Bit : 7 6 5 4 3 2 1 0
— — — PG4 PG3 PG2 PG1 PG0
Initial value : Undefined Undefined Undefined —
*
—
*
—
*
—
*
—
*
R/W : — — — R R R R R
Note: * Determined by state of pins PG
4
to PG
0
.
PORTG is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port G pins (PG
4
to PG
0
) must always be performed on PGDR.
Bits 7 to 5 are reserved; they return an undefined value if read, and cannot be modified.
If a port G read is performed while PGDDR bits are set to 1, the PGDR values are read. If a port G
read is performed while PGDDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTG contents are determined by the pin states, as
PGDDR and PGDR are initialized. PORTG retains its prior state in software standby mode.