Datasheet

Section 6 Bus Controller
Rev.6.00 Sep. 27, 2007 Page 206 of 1268
REJ09B0220-0600
Usage Notes: When DRAM space
*
is accessed, the ICIS0 and ICIS1 bit settings are disabled. In
the case of consecutive reads between different areas, for example, if the second access is a
DRAM access
*
, only a T
p
cycle is inserted, and a T
I
cycle is not. The timing in this case is shown
in figure 6.34.
However, in burst access in RAS down mode these settings are enabled, and an idle cycle is
inserted. The timing in this case is shown in figures 6.35 (a) and (b).
Note: * The DRAM interface is not supported in the H8S/2321.
T
1
A
ddress bus
φ
RD
External read
Data bus
T
2
T
3
T
p
T
r
DRAM space read
T
c1
T
c2
Figure 6.34 Example of DRAM Access after External Read