Datasheet

Appendix C I/O Port Block Diagrams
Rev.6.00 Sep. 27, 2007 Page 1220 of 1268
REJ09B0220-0600
R
P1nDDR
C
QD
Reset
WDDR1
Reset
WDR1
R
P1nDR
C
QD
P1
n
RDR1
RPOR1
Internal data bus
PPG module
TPU module
Pulse output enable
Output compare output
/
PWM output enable
Output compare output
/
PWM output
Pulse output
External clock input
Input capture input
Legend:
WDDR1: Write to P1DDR
WDR1: Write to P1DR
RDR1: Read P1DR
RPOR1: Read port 1
Note: n = 2, 3, 5, 7
Figure C.1 (b) Port 1 Block Diagram (Pins P1
2
, P1
3
, P1
5
, and P1
7
)