Datasheet

Appendix B Internal I/O Registers
Rev.6.00 Sep. 27, 2007 Page 1202 of 1268
REJ09B0220-0600
TIOR0H—Timer I/O Control Register 0H H'FFD2 TPU0
7
IOB3
0
R/W
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
IOA3
0
R/W
0
IOA0
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
0
1
TGR0B I/O Control
0
1
0
1
0
1
0
1
0
1
*
0
1
0
1
0
1
0
1
0
1
*
*
0
1
TGR0A
is output
compare
register
TGR0A I/O Control
0
1
0
1
0
1
0
1
0
1
*
0
1
0
1
0
1
0
1
0
1
*
*
Output disabled
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
* : Don’t care
* : Don’t care
Note: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and φ/1 is used as
the TCNT1 count clock, this setting is invalid and input capture does not occur.
Bit
Initial value
Read/Write
:
:
:
Initial output is
0 output
TGR0A
is input
capture
register
Output disabled
Initial output is
1 output
Capture input
source is
TIOCA
0
pin
Capture input
source is channel
1/count clock
Input capture at TCNT1 count-up/
count-down
TGR0B
is output
compare
register
Output disabled
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Initial output is
0 output
TGR0B
is input
capture
register
Output disabled
Initial output is
0 output
Capture input
source is
TIOCB
0
pin
Capture input
source is channel
1/count clock
Input capture at TCNT1 count-up/
count-down*
1