Datasheet

Appendix B Internal I/O Registers
Rev.6.00 Sep. 27, 2007 Page 1192 of 1268
REJ09B0220-0600
TCNT—Timer Counter H'FFBC (W), H'FFBD (R) WDT
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Bit
Initial value
Read/Write
:
:
:
RSTCSR—Reset Control/Status Register H'FFBE (W), H'FFBF (R) WDT
7
WOVF
0
R/(W)*
6
RSTE
0
R/W
5
—
0
R/W
4
—
1
—
3
—
1
—
0
—
1
—
2
—
1
—
1
—
1
—
0
1
[Clearing condition]
When 0 is written to WOVF after reading RSTCSR when WOVF = 1
Watchdog Timer Overflow Flag
0
1
Reset Enable
Reset signal is not generated if TCNT overflows*
Reset signal is generated if TCNT overflows
Reserved
This bit should be written with 0
Bit
Initial value
Read/Write
:
:
:
[Setting condition]
When TCNT overflows (changes from H'FF to H'00) during watchdog
timer operation
Note: * The modules in the H8S/2329 and H8S/2328 Groups are
not reset, but TCNT and TCSR in WDT are reset.
Note: * Can only be written with 0 for flag clearing.
The method for writing to RSTCSR is different from that for general registers to prevent accidental
overwriting. For details, see section 13.2.4, Notes on Register Access.