Datasheet

Appendix B Internal I/O Registers
Rev.6.00 Sep. 27, 2007 Page 1191 of 1268
REJ09B0220-0600
TCSR—Timer Control/Status Register H'FFBC (W), H'FFBC (R) WDT
Notes: 1. The method for writing to TCSR is different from that for general registers to prevent
accidental overwriting. For details, see section 13.2.4, Notes on Register Access.
2. Can only be written with 0 for flag clearing.
0 [Clearing condition]
When 0 is written to OVF after reading OVF = 1
1
Overflow Flag
0 Interval timer mode: Sends the CPU an interval timer interrupt
request (WOVI) when TCNT overflows
Watchdog timer mode: Generates the WDTOVF signal
*
1
when
TCNT overflows
*
2
1
Timer Mode Select
0
1
TCNT is initialized to H'00 and halted
TCNT counts
Timer Enable
Clock Select
CKS2
CKS1 CKS0 Clock
Overflow period*
(when φ = 20 MHz)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
φ/2 (Initial value)
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
25.6 µs
819.2 µs
1.6 ms
6.6 ms
26.2 ms
104.9 ms
419.4 ms
1.68 s
Note: * The overflow period is the time from when TCNT
starts counting up from H'00 until overflow occurs.
[Setting condition]
When TCNT overflows from H'FF to H'00 in interval timer mode
7
OVF
0
R/(W)
*
2
6
WT/IT
0
R/W
5
TME
0
R/W
4
—
1
—
3
—
1
—
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Bit
Initial value
Read/Write
*
1
:
:
:
Notes: 1. The WDTOVF pin function is not available in the F-ZTAT versions.
2. For details of the case where TCNT overflows in watchdog timer
mode, see section 13.2.3, Reset Control/Status Register (RSTCSR).