Datasheet

Appendix B Internal I/O Registers
Rev.6.00 Sep. 27, 2007 Page 1174 of 1268
REJ09B0220-0600
SMR2—Serial Mode Register 2 H'FF88 Smart Card Interface 2
7
GM
0
R/W
6
BLK
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
BCP1
0
R/W
0
CKS0
0
R/W
2
BCP0
0
R/W
1
CKS1
0
R/W
0
1
GSM Mode
0
1
Setting prohibited
Parity bit addition and checking enabled
Parity Enable
0
1
Even parity
Odd parity
Parity Mode
(Set to 1 when using the smart card interface)
0
1
0
1
0
1
φ clock
φ/4 clock
φ/16 clock
φ/64 clock
Clock Select
Bit
Initial value
Read/Write
:
:
:
Note: etu: Elementary time unit (time for transfer of 1 bit)
0
1
0
1
0
1
32 clocks
64 clocks
372 clocks
256 clocks
Base Clock Pulse
BCP1 BCP0
Base Clock Pulse
0
1
Normal smart card interface mode
Block transfer mode
Block Transfer Mode Select
Normal smart card interface mode operation
• TEND flag generated 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit
• C
lock output on/off control only
GSM mode smart card interface mode operation
• TEND flag generated 11.0 etu after beginning of start bit
• Fixed high/low-level control possible (set in SCR) in addition to clock output on
/off control