Datasheet

Appendix B Internal I/O Registers
Rev.6.00 Sep. 27, 2007 Page 1155 of 1268
REJ09B0220-0600
SMR0—Serial Mode Register 0 H'FF78 SCI0
7
C/A
0
R/W
6
CHR
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
STOP
0
R/W
0
CKS0
0
R/W
2
MP
0
R/W
1
CKS1
0
R/W
0
1
Asynchronous mode
Synchronous mode
Asynchronous Mode/Synchronous Mode Select
0
1
Parity bit addition and checking disabled
Parity bit addition and checking enabled
Parity Enable
0
1
Even parity
Odd parity
Parity Mode
0
1
0
1
0
1
φ clock
φ/4 clock
φ/16 clock
φ/64 clock
Clock Select
Bit
Initial value
Read/Write
:
:
:
0
1
Multiprocessor function
disabled
Multiprocessor format
selected
Multiprocessor Mode
0
1
1 stop bit
2 stop bits
Stop Bit Length
0
1
8-bit data
7-bit data*
Character Length
Note: * When 7-bit data is selected, the MSB (bit 7)
of TDR is not transmitted.