Datasheet

Appendix B Internal I/O Registers
Rev.6.00 Sep. 27, 2007 Page 1130 of 1268
REJ09B0220-0600
DTCERA to DTCERF—DTC Enable Registers H'FF30 to H'FF35 DTC
7
DTCE7
0
R/W
6
DTCE6
0
R/W
5
DTCE5
0
R/W
4
DTCE4
0
R/W
3
DTCE3
0
R/W
0
DTCE0
0
R/W
2
DTCE2
0
R/W
1
DTCE1
0
R/W
DTC Activation Enable
Bit
Initial value
Read/Write
:
:
:
DTC activation by this interrupt is disabled
[Clearing conditions]
• When the DISEL bit is 1 and data transfer has ended
• When the specified number of transfers have ended
0
1 DTC activation by this interrupt is enabled
[Holding condition]
When the DISEL bit is 0 and the specified number of
transfers have not ended
Correspondence between Interrupt Sources and DTCER
Bits
Register 7 6 5 4 3 2 1 0
DTCERA IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
DTCERB — ADI TGI0A TGI0B TGI0C TGI0D TGI1A TGI1B
DTCERC TGI2A TGI2B TGI3A TGI3B TGI3C TGI3D TGI4A TGI4B
DTCERD — — TGI5A TGI5B CMIA0 CMIB0 CMIA1 CMIB1
DTCERE DMTEND0A DMTEND0B DMTEND1A DMTEND1B RXI0 TXI0 RXI1 TXI1
DTCERF RXI2 TXI2 — — — — — —
Note: For DTCE bit setting, read/write operations must be performed using bit-manipulation
instructions such as BSET and BCLR. For the initial setting only, however, when multiple
activation sources are set at one time, it is possible to disable interrupts and write after
executing a dummy read on the relevant register.