Datasheet

Appendix B Internal I/O Registers
Rev.6.00 Sep. 27, 2007 Page 1095 of 1268
REJ09B0220-0600
TIOR5—Timer I/O Control Register 5 H'FEA2 TPU5
7
IOB3
0
R/W
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
IOA3
0
R/W
0
IOA0
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
Bit
Initial value
Read/Write
:
:
:
0
1
TGR5B I/O Control
0
1
*
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
*
0
1
TGR5A
is output
compare
register
TGR5A I/O Control
0
1
*
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
*
Output disabled
0 output at compare match
1 output at compare match
Toggle output at compare match
* : Don’t care
TGR5A
is input
capture
register
Initial output is 0
output
Output disabled
0 output at compare match
1 output at compare match
Toggle output at compare match
Initial output is 1
output
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Capture input
source is TIOCA
5
pin
TGR5B
is output
compare
register
Output disabled
0 output at compare match
1 output at compare match
Toggle output at compare match
* : Don’t care
TGR5B
is input
capture
register
Initial output is 0
output
Output disabled
0 output at compare match
1 output at compare match
Toggle output at compare match
Initial output is 1
output
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Capture input
source is TIOCB
5
pin