Datasheet

Appendix B Internal I/O Registers
Rev.6.00 Sep. 27, 2007 Page 1093 of 1268
REJ09B0220-0600
TCR5—Timer Control Register 5 H'FEA0 TPU5
TCNT clearing disabled
TCNT cleared by TGRA compare match/input capture
TCNT cleared by TGRB compare match/input capture
Counter Clear
0
1
0
1
0
1
Internal clock: counts on φ /1
Internal clock: counts on
φ /4
Internal clock: counts on
φ /16
Internal clock: counts on
φ /64
External clock: counts on TCLKA pin input
External clock: counts on TCLKC pin input
Internal clock: counts on
φ /256
External clock: counts on TCLKD pin input
Time Prescaler
0
1
0
1
0
1
0
1
0
1
0
1
0
1
7
—
0
—
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
0
TPSC0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
Bit
Initial value
Read/Write
:
:
:
Note:
0
1
Clock Edge
0
1
—
Count at rising edge
Count at falling edge
Count at both edges
This setting is ignored when channel 5 is in phase
counting mode.
Note: * Synchronous operation setting is performed by setting
the SYNC bit in TSYR to 1.
Note: This setting is ignored when channel
5 is in phase counting mode.
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation*