Datasheet

Section 22 Electrical Characteristics
Rev.6.00 Sep. 27, 2007 Page 974 of 1268
REJ09B0220-0600
(5) Timing of On-Chip Supporting Modules
Table 22.19 Timing of On-Chip Supporting Modules
Condition B: V
CC
= 3.0 V to 3.6 V, AV
CC
= 3.0 V to 3.6 V, V
ref
= 3.0 V to AV
CC
, V
SS
= AV
SS
=
0 V, φ = 2 MHz to 25 MHz, T
a
= –20°C to 75°C (regular specifications),
T
a
= –40°C to 85°C (wide-range specifications)
Condition B
Item Symbol Min Max Unit Test Conditions
I/O ports Output data delay time t
PWD
— 40 ns Figure 22.20
Input data setup time t
PRS
25 —
Input data hold time t
PRH
25 —
PPG Pulse output delay time t
POD
— 40 ns Figure 22.21
TPU Timer output delay time t
TOCD
— 40 ns Figure 22.22
Timer input setup time t
TICS
25 —
Timer clock input setup time t
TCKS
25 — ns Figure 22.23
Timer clock
pulse width
Single-edge
specification
t
TCKWH
1.5 — t
cyc
Both-edge
specification
t
TCKWL
2.5 —
8-bit timer Timer output delay time t
TMOD
— 40 ns Figure 22.24
Timer reset input setup time t
TMRS
25 — ns Figure 22.26
Timer clock input setup time t
TMCS
25 — ns Figure 22.25
Timer clock
pulse width
Single-edge
specification
t
TMCWH
1.5 — t
cyc
Both-edge
specification
t
TMCWL
2.5 —
SCI Asynchronous t
Scyc
4 — t
cyc
Figure 22.28
Input clock
cycle
Synchronous 6 —
Input clock pulse width t
SCKW
0.4 0.6 t
Scyc
Input clock rise time t
SCKr
— 1.5 t
cyc
Input clock fall time t
SCKf
— 1.5
Transmit data delay time t
TXD
— 40 ns Figure 22.29
Receive data setup time
(synchronous)
t
RXS
40 — ns
Receive data hold time
(synchronous)
t
RXH
40 — ns
A/D
converter
Trigger input setup time t
TRGS
30 — ns Figure 22.30